Chapter 11 – Running the simulation

To run the simulation, we simply execute the provided Makefile in the GitHub repository:

$ make -f Makefile.vcs

The testbench will generate random inputs and then those inputs will be sent to the DUT. The monitors will capture the data in the communication bus and make a prediction of the expected result. Finally the scoreboard will evaluate the functionality by matching the DUT’s response with the prediction made by one of the monitors. If the DUT and the prediction match, an “OK” message will be outputted, otherwise, we will se a “Fail” message.

So, in the output of the simulation, we must find for the messages starting with UVM_INFO because the compare() method from the scoreboard is going to print a message using the macro `uvm_info() with the result of the test.

The result of the simulation can be seen below:

***********       IMPORTANT RELEASE NOTES         ************

You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test simpleadder_test…
UVM_INFO simpleadder_scoreboard.sv(49) @ 70: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 130: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 190: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 250: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 310: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 370: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 430: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 490: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 550: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 610: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 670: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 730: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 790: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO simpleadder_scoreboard.sv(49) @ 850: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
UVM_INFO ../uvm-src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 900: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

— UVM Report Summary —

** Report counts by severity
UVM_INFO :   16
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[TEST_DONE]     1
[compare]    14
$finish called from file “../uvm-src/uvm-1.1d/src/base/uvm_root.svh”, line 430.
$finish at simulation time                  900
V C S   S i m u l a t i o n   R e p o r t
Time: 900 ns
CPU Time:      2.040 seconds;       Data structure size:   0.2Mb

 

This chapter concludes this beginner’s guide. You can access all the code in this repository.

17 thoughts to “Chapter 11 – Running the simulation”

    1. Hello Yue,

      Unfortunately I don’t have access to a license of QuestaSim and the Makefile is made for VCS, but it should be easy to make it work of QuestaSim.

      I’ll try to look into it as soon I finish my thesis.

      1. Hi, I just make it through under the questa. But I got the following results maybe it’s not same with yours. Why?

        # You are using a version of the UVM library that has been compiled
        # with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
        # See http://www.eda.org/svdb/view.php?id=3770 for more details.
        #
        # (Specify +UVM_NO_RELNOTES to turn off this notice)
        #
        # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.2
        # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
        # UVM_INFO @ 0: reporter [RNTST] Running test simpleadder_test…
        # UVM_INFO ../src/adder.sv(377) @ 70: uvm_test_top.sa_env.sa_sb [compare] Test: OK!
        # UVM_INFO ../src/adder.sv(379) @ 130: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 190: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 250: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 310: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 370: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 430: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 490: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 550: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 610: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 670: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 730: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 790: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO ../src/adder.sv(379) @ 850: uvm_test_top.sa_env.sa_sb [compare] Test: Fail!
        # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 900: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

        1. Yue,

          Is it possible to send me a copy of your makefile please?

          Can you also send the code, that you edited, to me? It’s really hard to make anything out of wordpress comments.

        2. Hi Yue,
          I got the error resolved by including few modification only to the class “simpladder_monitor_before” under the run_phase in forever loop statement

          if (state ==3)
          begin
          sa_tx.out = sa_tx.out << 1;
          if (counter_mon==3) // newly included
          begin // newly included
          sa_tx.out[0]=vif.sig_out; // newly included
          end // newly included
          counter_mon=counter_mon+1;
          if (counter_mon==3)
          begin
          state=0;
          counter_mon=0;
          mon_ap_before.write(sa_tx);
          end
          end

          The issue "TEST fail" occurred due to the output from DUT was not delayed enough to sync with the predictor() output from the simpleadder_monitor_after. After adding a 2 clock cycle additional delay to sig_out before it reach the scoreboard the results become PASS.

          Hi Pedro,

          Please correct me if tried something wrong to make the test pass :)

          Thanks
          Prasanna

      2. and the following is the code I changed a little.

        `include “uvm_macros.svh”

        interface simpleadder_if;
        logic sig_clock;
        logic sig_ina;
        logic sig_inb;
        logic sig_en_i;

        logic sig_out;
        logic sig_en_o;
        endinterface: simpleadder_if
        //////////////////////////////////////////////////
        //////////////////////////////////////////////////
        package simpleadder_pkg;
        import uvm_pkg::*;

        //////////////////////////////////////////////////
        ///////////////////////////////////////////
        class simpleadder_configuration extends uvm_object;
        `uvm_object_utils(simpleadder_configuration)

        function new(string name = “”);
        super.new(name);
        endfunction: new
        endclass: simpleadder_configuration
        //////////////////////////////////////////////////
        //////////////////////////////////////////
        class simpleadder_transaction extends uvm_sequence_item;
        rand bit[1:0] ina;
        rand bit[1:0] inb;
        bit[2:0] out;

        function new(string name = “”);
        super.new(name);
        endfunction: new

        `uvm_object_utils_begin(simpleadder_transaction)
        `uvm_field_int(ina, UVM_ALL_ON)
        `uvm_field_int(inb, UVM_ALL_ON)
        `uvm_field_int(out, UVM_ALL_ON)
        `uvm_object_utils_end
        endclass: simpleadder_transaction

        class simpleadder_sequence extends uvm_sequence#(simpleadder_transaction);
        `uvm_object_utils(simpleadder_sequence)

        function new(string name = “”);
        super.new(name);
        endfunction: new

        task body();
        simpleadder_transaction sa_tx;

        repeat(5) begin
        sa_tx = simpleadder_transaction::type_id::create(.name(“sa_tx”), .contxt(get_full_name()));

        start_item(sa_tx);
        assert(sa_tx.randomize());
        //`uvm_info(“sa_sequence”, sa_tx.sprint(), UVM_LOW);
        finish_item(sa_tx);
        end
        endtask: body
        endclass: simpleadder_sequence

        typedef uvm_sequencer#(simpleadder_transaction) simpleadder_sequencer;

        //////////////////////////////////////////////////////////////
        ///////////////////////////////////////////////////////////////
        class simpleadder_driver extends uvm_driver#(simpleadder_transaction);
        `uvm_component_utils(simpleadder_driver)

        virtual simpleadder_if vif;

        function new(string name, uvm_component parent);
        super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        void'(uvm_resource_db#(virtual simpleadder_if)::read_by_name
        (.scope(“ifs”), .name(“simpleadder_if”), .val(vif)));
        endfunction: build_phase

        task run_phase(uvm_phase phase);
        drive();
        endtask: run_phase

        virtual task drive();
        simpleadder_transaction sa_tx;
        integer counter = 0, state = 0;
        vif.sig_ina = 0’b0;
        vif.sig_inb = 0’b0;
        vif.sig_en_i = 1’b0;

        forever begin
        if(counter==0)
        begin
        seq_item_port.get_next_item(sa_tx);
        //`uvm_info(“sa_driver”, sa_tx.sprint(), UVM_LOW);
        end

        @(posedge vif.sig_clock)
        begin
        if(counter==0)
        begin
        vif.sig_en_i = 1’b1;
        state = 1;
        end

        if(counter==1)
        begin
        vif.sig_en_i = 1’b0;
        end

        case(state)
        1: begin
        vif.sig_ina = sa_tx.ina[1];
        vif.sig_inb = sa_tx.inb[1];

        sa_tx.ina = sa_tx.ina << 1;
        sa_tx.inb = sa_tx.inb << 1;

        counter = counter + 1;
        if(counter==2) state = 2;
        end

        2: begin
        vif.sig_ina = 1'b0;
        vif.sig_inb = 1'b0;
        counter = counter + 1;

        if(counter==6)
        begin
        counter = 0;
        state = 0;
        seq_item_port.item_done();
        end
        end
        endcase
        end
        end
        endtask: drive
        endclass: simpleadder_driver
        /////////////////////////////////////////////////////////////////
        ////////////////////////////////////////////////////////////
        class simpleadder_monitor_before extends uvm_monitor;
        `uvm_component_utils(simpleadder_monitor_before)

        uvm_analysis_port#(simpleadder_transaction) mon_ap_before;

        virtual simpleadder_if vif;

        function new(string name, uvm_component parent);
        super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        void'(uvm_resource_db#(virtual simpleadder_if)::read_by_name
        (.scope("ifs"), .name("simpleadder_if"), .val(vif)));
        mon_ap_before = new(.name("mon_ap_before"), .parent(this));
        endfunction: build_phase

        task run_phase(uvm_phase phase);
        integer counter_mon = 0, state = 0;

        simpleadder_transaction sa_tx;
        sa_tx = simpleadder_transaction::type_id::create
        (.name("sa_tx"), .contxt(get_full_name()));

        forever begin
        @(posedge vif.sig_clock)
        begin
        if(vif.sig_en_o==1'b1)
        begin
        state = 3;
        end

        if(state==3)
        begin
        sa_tx.out = sa_tx.out << 1;
        sa_tx.out[0] = vif.sig_out;

        counter_mon = counter_mon + 1;

        if(counter_mon==3)
        begin
        state = 0;
        counter_mon = 0;

        //Send the transaction to the analysis port
        mon_ap_before.write(sa_tx);
        end
        end
        end
        end
        endtask: run_phase
        endclass: simpleadder_monitor_before

        class simpleadder_monitor_after extends uvm_monitor;
        `uvm_component_utils(simpleadder_monitor_after)

        uvm_analysis_port#(simpleadder_transaction) mon_ap_after;

        virtual simpleadder_if vif;

        simpleadder_transaction sa_tx;

        //For coverage
        simpleadder_transaction sa_tx_cg;

        //Define coverpoints
        covergroup simpleadder_cg;
        ina_cp: coverpoint sa_tx_cg.ina;
        inb_cp: coverpoint sa_tx_cg.inb;
        cross ina_cp, inb_cp;
        endgroup: simpleadder_cg

        function new(string name, uvm_component parent);
        super.new(name, parent);
        simpleadder_cg = new;
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        void'(uvm_resource_db#(virtual simpleadder_if)::read_by_name
        (.scope("ifs"), .name("simpleadder_if"), .val(vif)));
        mon_ap_after= new(.name("mon_ap_after"), .parent(this));
        endfunction: build_phase

        task run_phase(uvm_phase phase);
        integer counter_mon = 0, state = 0;
        sa_tx = simpleadder_transaction::type_id::create
        (.name("sa_tx"), .contxt(get_full_name()));

        forever begin
        @(posedge vif.sig_clock)
        begin
        if(vif.sig_en_i==1'b1)
        begin
        state = 1;
        sa_tx.ina = 2'b00;
        sa_tx.inb = 2'b00;
        sa_tx.out = 3'b000;
        end

        if(state==1)
        begin
        sa_tx.ina = sa_tx.ina << 1;
        sa_tx.inb = sa_tx.inb << 1;

        sa_tx.ina[0] = vif.sig_ina;
        sa_tx.inb[0] = vif.sig_inb;

        counter_mon = counter_mon + 1;

        if(counter_mon==2)
        begin
        state = 0;
        counter_mon = 0;

        //Predict the result
        predictor();
        sa_tx_cg = sa_tx;

        //Coverage
        simpleadder_cg.sample();

        //Send the transaction to the analysis port
        mon_ap_after.write(sa_tx);
        end
        end
        end
        end
        endtask: run_phase

        virtual function void predictor();
        sa_tx.out = sa_tx.ina + sa_tx.inb;
        endfunction: predictor
        endclass: simpleadder_monitor_after
        ////////////////////////////////////////////////////////////////////
        /////////////////////////////////////////////////////////////
        class simpleadder_agent extends uvm_agent;
        `uvm_component_utils(simpleadder_agent)

        uvm_analysis_port#(simpleadder_transaction) agent_ap_before;
        uvm_analysis_port#(simpleadder_transaction) agent_ap_after;

        simpleadder_sequencer sa_seqr;
        simpleadder_driver sa_drvr;
        simpleadder_monitor_before sa_mon_before;
        simpleadder_monitor_after sa_mon_after;

        function new(string name, uvm_component parent);
        super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        agent_ap_before = new(.name("agent_ap_before"), .parent(this));
        agent_ap_after = new(.name("agent_ap_after"), .parent(this));

        sa_seqr = simpleadder_sequencer::type_id::create(.name("sa_seqr"), .parent(this));
        sa_drvr = simpleadder_driver::type_id::create(.name("sa_drvr"), .parent(this));
        sa_mon_before = simpleadder_monitor_before::type_id::create(.name("sa_mon_before"), .parent(this));
        sa_mon_after = simpleadder_monitor_after::type_id::create(.name("sa_mon_after"), .parent(this));
        endfunction: build_phase

        function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);

        sa_drvr.seq_item_port.connect(sa_seqr.seq_item_export);
        sa_mon_before.mon_ap_before.connect(agent_ap_before);
        sa_mon_after.mon_ap_after.connect(agent_ap_after);
        endfunction: connect_phase
        endclass: simpleadder_agent
        ///////////////////////////////////////////////////////////////
        //////////////////////////////////////////////////////////
        // //
        `uvm_analysis_imp_decl(_before)
        `uvm_analysis_imp_decl(_after)

        class simpleadder_scoreboard extends uvm_scoreboard;
        `uvm_component_utils(simpleadder_scoreboard)

        uvm_analysis_export #(simpleadder_transaction) sb_export_before;
        uvm_analysis_export #(simpleadder_transaction) sb_export_after;

        uvm_tlm_analysis_fifo #(simpleadder_transaction) before_fifo;
        uvm_tlm_analysis_fifo #(simpleadder_transaction) after_fifo;

        simpleadder_transaction transaction_before;
        simpleadder_transaction transaction_after;

        function new(string name, uvm_component parent);
        super.new(name, parent);

        transaction_before = new("transaction_before");
        transaction_after = new("transaction_after");
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        sb_export_before = new("sb_export_before", this);
        sb_export_after = new("sb_export_after", this);

        before_fifo = new("before_fifo", this);
        after_fifo = new("after_fifo", this);
        endfunction: build_phase

        function void connect_phase(uvm_phase phase);
        sb_export_before.connect(before_fifo.analysis_export);
        sb_export_after.connect(after_fifo.analysis_export);
        endfunction: connect_phase

        task run();
        forever begin
        before_fifo.get(transaction_before);
        after_fifo.get(transaction_after);

        compare();
        end
        endtask: run

        virtual function void compare();
        if(transaction_before.out == transaction_after.out) begin
        `uvm_info("compare", {"Test: OK!"}, UVM_LOW);
        end else begin
        `uvm_info("compare", {"Test: Fail!"}, UVM_LOW);
        end
        endfunction: compare
        endclass: simpleadder_scoreboard
        ///////////////////////////////////////////////////////////////
        class simpleadder_env extends uvm_env;
        `uvm_component_utils(simpleadder_env)

        simpleadder_agent sa_agent;
        simpleadder_scoreboard sa_sb;

        function new(string name, uvm_component parent);
        super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        sa_agent = simpleadder_agent::type_id::create(.name("sa_agent"), .parent(this));
        sa_sb = simpleadder_scoreboard::type_id::create(.name("sa_sb"), .parent(this));
        endfunction: build_phase

        function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
        sa_agent.agent_ap_before.connect(sa_sb.sb_export_before);
        sa_agent.agent_ap_after.connect(sa_sb.sb_export_after);
        endfunction: connect_phase
        endclass: simpleadder_env
        /////////////////////////////////////////////////////////
        class simpleadder_test extends uvm_test;
        `uvm_component_utils(simpleadder_test)

        simpleadder_env sa_env;

        function new(string name, uvm_component parent);
        super.new(name, parent);
        endfunction: new

        function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        sa_env = simpleadder_env::type_id::create(.name("sa_env"), .parent(this));
        endfunction: build_phase

        task run_phase(uvm_phase phase);
        simpleadder_sequence sa_seq;

        phase.raise_objection(.obj(this));
        sa_seq = simpleadder_sequence::type_id::create(.name("sa_seq"), .contxt(get_full_name()));
        assert(sa_seq.randomize());
        sa_seq.start(sa_env.sa_agent.sa_seqr);
        phase.drop_objection(.obj(this));
        endtask: run_phase
        endclass: simpleadder_test
        endpackage

        ////////////////////////////////////////////////////////
        //
        module simpleadder(input wire clk,

        input wire en_i,
        input wire ina,
        input wire inb,

        output reg en_o,
        output reg out);

        integer counter, state;
        reg[1:0] temp_a, temp_b;
        reg[2:0] temp_out;

        //Init
        initial begin
        counter = 0;
        temp_a = 2'b00;
        temp_b = 2'b00;
        temp_out = 3'b000;
        out = 0;

        en_o <= 0;
        state = 0;
        end

        always@(posedge clk)
        begin
        //State 0: Wait for en_i
        if(en_i==1'b1)
        begin
        state = 1;
        end

        case(state)
        //State 1: Start reading inputs
        1: begin
        temp_a = temp_a << 1;
        temp_a = temp_a | ina;

        temp_b = temp_b << 1;
        temp_b = temp_b | inb;

        counter = counter + 1;

        //After 2 bits, do the operation an move to the next state
        if(counter==2) begin
        temp_out = temp_a + temp_b;

        state = 2;
        end
        end

        //State 2: Enable en_o and sends result to the output
        2: begin
        out <= temp_out[2];
        temp_out = temp_out << 1;

        counter = counter + 1;

        if(counter==3) en_o <= 1'b1;

        if(counter==4) en_o <= 1'b0;

        if(counter==6) begin
        counter = 0;
        out <= 1'b0;
        state = 0;
        end
        end
        endcase
        end
        endmodule
        /////////////////////////////////////////////////////////
        //
        module simpleadder_tb_top;
        import uvm_pkg::*;
        import simpleadder_pkg::*;

        //Interface declaration
        simpleadder_if vif();

        //Connects the Interface to the DUT
        simpleadder dut(vif.sig_clock,
        vif.sig_en_i,
        vif.sig_ina,
        vif.sig_inb,
        vif.sig_en_o,
        vif.sig_out);

        initial begin
        //Registers the Interface in the configuration block so that other
        //blocks can use it
        uvm_resource_db#(virtual simpleadder_if)::set
        (.scope("ifs"), .name("simpleadder_if"), .val(vif));

        //Executes the test
        run_test();
        end

        //Variable initialization
        initial begin
        vif.sig_clock <= 1'b1;
        end

        //Clock generation
        always
        #5 vif.sig_clock = ~vif.sig_clock;
        endmodule
        ////////////////////////////////////////////////////////////

  1. Hi Pedro,

    I too get the same error messages as posted by Yue Li. I used questasim 10.1c for simulation. Didn’t do any modification to your original source code.

    Thanks
    Prasanna

  2. Dear Pedro,

    Can you please upload the results (snapshot of the waveform) of the DUT drive by simpleadder_directtb_driver.v ? It shows error at line 111.

    Regards,
    Vishal

  3. Hi Pedro,

    I install questasim in windows can you show me how can I can simulation. Shall I must install Questasim in linux to run ?

    Thank for your support

  4. Hey,
    I got this report on VCS log. Please help me with that.

    UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type ‘simpleadder_test’ because it is not registered with the factory.
    UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=simpleadder_test not found.

    1. try to modify simpleadder_tb_top.sv
      module simpleadder_tb_top;
      import uvm_pkg::*;
      import simpleadder_pkg::*;

      endmodule

      As a beginner to uvm, it spent me 3 hours and finally got the answer from my friend.

  5. compiled fine once I located proper UVM directories in vcs. Able to see UVM functions in dve as well as waveforms. Thanks much

  6. mvlog: *E,FAABP1 (simpleadder_test.sv,12|11): Task/function call, or property/sequence instance does not specify all required formal arguments.
    super.new(name);
    |
    xmvlog: *E,FAABP2 (simpleadder_test.sv,12|11): Formal argument ‘parent’ is missing in the task/function call or property/sequence instance identified by the previous error message.
    sa_seq = simpleadder_sequence::type_id::create(.name(“sa_seq”), .contxt(get_full_name()));
    |
    xmvlog: *E,UNDIDN (simpleadder_test.sv,34|9): ‘sa_seq’: undeclared identifier [12.5(IEEE)].
    assert(sa_seq.randomize());
    |
    xmvlog: *E,ILLHIN (simpleadder_test.sv,36|16): illegal location for a hierarchical name (in a package).
    sa_seq.start(sa_env.sa_agent.sa_seqr);
    |
    xmvlog: *E,ILLHIN (simpleadder_test.sv,38|15): illegal location for a hierarchical name (in a package).
    package worklib.simpleadder_pkg:sv
    errors: 5, warnings: 0
    file: simpleadder_tb_top.sv
    super.new(name);
    |
    xmvlog: *E,FAABP1 (./simpleadder_test.sv,12|11): Task/function call, or property/sequence instance does not specify all required formal arguments.
    (`include file: simpleadder_pkg.sv line 25, file: simpleadder_tb_top.sv line 1)
    super.new(name);
    |
    xmvlog: *E,FAABP2 (./simpleadder_test.sv,12|11): Formal argument ‘parent’ is missing in the task/function call or property/sequence instance identified by the previous error message.
    (`include file: simpleadder_pkg.sv line 25, file: simpleadder_tb_top.sv line 1)
    sa_seq = simpleadder_sequence::type_id::create(.name(“sa_seq”), .contxt(get_full_name()));
    |
    xmvlog: *E,UNDIDN (./simpleadder_test.sv,34|9): ‘sa_seq’: undeclared identifier [12.5(IEEE)].
    (`include file: simpleadder_pkg.sv line 25, file: simpleadder_tb_top.sv line 1)
    assert(sa_seq.randomize());
    |
    xmvlog: *E,ILLHIN (./simpleadder_test.sv,36|16): illegal location for a hierarchical name (in a package).
    (`include file: simpleadder_pkg.sv line 25, file: simpleadder_tb_top.sv line 1)
    sa_seq.start(sa_env.sa_agent.sa_seqr);
    |
    xmvlog: *E,ILLHIN (./simpleadder_test.sv,38|15): illegal location for a hierarchical name (in a package).
    (`include file: simpleadder_pkg.sv line 25, file: simpleadder_tb_top.sv line 1)
    package worklib.simpleadder_pkg:sv
    errors: 5, warnings: 0
    file: simpleadder_test.sv
    class simpleadder_test extends uvm_test;
    |
    xmvlog: *E,SVNOTY (simpleadder_test.sv,1|38): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,SVNOTY (simpleadder_test.sv,3|39): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,SVEXTK (simpleadder_test.sv,3|39): expecting a ‘;’ (to terminate a type_declaration).
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,SVEXTK (simpleadder_test.sv,3|39): expecting a ‘;’ (to terminate a type_declaration).
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,SVNOTY (simpleadder_test.sv,3|39): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,EXPSMC (simpleadder_test.sv,3|39): expecting a semicolon (‘;’) [10.3.1(IEEE)].
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,SVNOTY (simpleadder_test.sv,3|39): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    `uvm_component_utils(simpleadder_test)
    |
    xmvlog: *E,EXPSMC (simpleadder_test.sv,3|39): expecting a semicolon (‘;’) [10.3.1(IEEE)].
    (`define macro: m_uvm_component_registry_internal [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/opt/xcelium_19.03.007/CEN/tools/methodology/UVM/CDNS-1.1d/sv/src/macros/uvm_object_defines.svh line 330], file: simpleadder_test.sv line 3)
    simpleadder_env sa_env;
    |
    xmvlog: *E,NOIPRT (simpleadder_test.sv,5|22): Unrecognized declaration ‘simpleadder_env’ could be an unsupported keyword, a spelling mistake or missing instance port list ‘()’ [SystemVerilog].
    simpleadder_sequencer sa_seqr;
    |
    xmvlog: *E,NOIPRT (simpleadder_test.sv,6|28): Unrecognized declaration ‘simpleadder_sequencer’ could be an unsupported keyword, a spelling mistake or missing instance port list ‘()’ [SystemVerilog].
    super.new(name);
    |
    xmvlog: *E,CLSSPX (simpleadder_test.sv,12|7): ‘super’ can only be used within a class scope that derives from a base class.
    function void build_phase(uvm_phase phase);
    |
    xmvlog: *E,SVNOTY (simpleadder_test.sv,18|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    task run_phase(uvm_phase phase);
    |
    xmvlog: *E,SVNOTY (simpleadder_test.sv,28|25): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
    Total errors/warnings found outside modules and primitives:
    errors: 13, warnings: 0
    xrun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
    TOOL: xrun 19.03-s007: Exiting on Aug 13, 2019 at 18:11:15 CEST (total: 00:00:01)
    I am getting many errors when compiling with the linux

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