UVM Guide for Beginners

Due to the lack of UVM tutorials for complete beginners, I decided to create a guide that will assist a novice in building a verification environment using this methodology. I will not focus on verification techniques nor in the best practices in verifying a digital design, this guide was thought in helping you to understand the UVM API and in helping you to successfully compile a complete environment.

The simulator used is Synopsys VCS but the testbench should compile in any HDL simulator that supports SystemVerilog.

The code for the environment can be download in this GitHub repository: https://github.com/pedro-araujo/uvm-testbench-tutorial-simple-adder

Introduction

As digital systems grow in complexity, verification methodologies get progressively more essential. While in the early beginnings, digital designs were verified by looking at waveforms and performing manual checks, the complexity we have today don’t allow for that kind of verification anymore and, as a result, designers have been trying to find the best way to automate this process.

The SystemVerilog language came to aid many verification engineers. The language featured some mechanisms, like classes, covergroups and constraints, that eased some aspects of verifying a digital design and then, verification methodologies started to appear.

UVM is one of the methodologies that were created from the need to automate verification. The Universal Verification Methodology is a collection of API and proven verification guidelines written for SystemVerilog that help an engineer to create an efficient verification environment. It’s an open-source standard maintained by Accellera and can be freely acquired in their website.

By mandating a universal convention in verification techniques, engineers started to develop generic verification components that were portable from one project to another, this promoted the cooperation and the sharing of techniques among the user base. It also encouraged the development of verification components generic enough to be easily extended and improved without modifying the original code.

All these aspects contributed for a reduced effort in developing new verification environments, as designers can just reuse testbenches from previous projects and easily modify the components to their needs.

These series of webpages will provide a training guide for verifying a basic adder block using UVM. The guide will assume that you have some basic knowledge of SystemVerilog and will require accompaniment of the following resources:

This guide will be divided in 3 different parts:

  • The first part, starting on chapter 1, will explain the operation of the device under test (DUT): the inputs, the outputs and the communication bus
  • The second part, starting on chapter 2, will give a brief overview of a generic verification environment and the approach into verifying the DUT
  • The third part, starting on chapter 3, will start to describe a possible UVM testbench to be used with our DUT with code examples. It’s important to consult to the external material in order to better understand the mechanism behind the testbench.

50 thoughts on “UVM Guide for Beginners

  1. Muito obrigado por compartilhar, Pedro. Seu tutorial ficou muito bom! Parabéns pela iniciativa.

  2. Hi,

    I’m not able to run your example QuestaSim 10.2b.

    Is it possible for you to provide a Makefile.questa for this example?

    Thanks
    /Sachin

  3. Hi Pedro,

    I’m unable to run your example using Modelsim.
    Could you pls provide me a MTI makefile for the same example?

    Thanks
    /Sachin

    1. Hi Sachin,
      Basically Modelsim wont support UVM and if you are having a trial version of Questasim then you wont be able to run UVM. If you are having orginal licence then you have to download UVM library from Accelera.

  4. You are awesome Pedro .I guess this is the first material I have ever seen simplified. ..please start a tutorial on this with more examples.

  5. Hi Pedro,
    Thanks for a very nice tutorial.
    I tried running your code on edaplayground
    I am getting some error there
    # UVM_FATAL @ 0: reporter [NOCOMP] No components instantiated. You must either instantiate at least one component before calling run_test or use run_test to do so. To run a test using run_test, use +UVM_TESTNAME or supply the test name in the argument to run_test(). Exiting simulation.
    I can share my session with you.
    http://www.edaplayground.com/x/pS#
    Can you take a look and let me know.
    In Edaplayground you can have max 10 files so I have clubbed together monitor code with agent.

    1. Hello vidya,

      I noticed that you commented the test block and the sequencer block. Those two are essential to the testbench, they cannot be removed.

      But you can remove the configuration block, it’s not useful for this tutorial. You can also copy the contents of “simpleradder_pkg.sv” to the top block and remove the file.

      I’ll update the guide very soon in order to keep it simpler and clearer.

      So to sum up:
      – Remove the “simpleradder_pkg.sv” and the “simpleadder_config.sv” files;

      – Replace the the files “simpleadder_tb_top.sv” and “simpleadder_test.sv” with the following ones:
      simpleadder_tb_top.sv – https://cloud.colorlesscube.com/f/0071c8958f/
      simpleadder_test.sv – https://cloud.colorlesscube.com/f/096861d2b5/

      – Keep your modification to the monitor and be sure to add your monitor file to the simpleadder_tb_top.sv;

      – Also, it seems that EDA Playground doesn’t support the randomize() method that it’s used by UVM: http://eda-playground.readthedocs.org/en/latest/modelsim-uvm.html#modelsim-uvm
      Follow the instructions in that link (you just need to add the line “do_not_randomize = 1’b1;” to the constructor of the class simpleadder_transaction).

      If you follow these instructions, this testbench should be able to compile on EDA Playground.

      Please let me know if it worked. If you have any other questions, I’m happy to help. :)

    2. Did you resolve your problem ? I have the same one… No entity is found during the compilation …. what happen ?

      Someone has been luky with modelsim (or questa) and this UVM environment ?

      Thx

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  6. Hello Pedro Araujo, thanks for making such a informative tutorial, it helped me alot. Please add more of them. I’ll wait for it.
    and Just in case if it helps, i want to add if you are using questa then you have to make an instance of the “test class” in the top module and then the error of “NO component” instantiated will be removed and the test will be able to run
    Thanks.

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  8. Hi Pedro,

    1, First of all, thank you so much for writing such a comprehensive guild for a UVM beginer.

    2, I am trying to run the simpleradder example. I got a simulation error that is complaining about the simpleradder_monitor.sv, when it call the virtual function void predictor(); The message is like below:

    Error-[NOA] Null object access
    simpleadder_monitor.sv, 127
    The object is being used before it was constructed/allocated.
    Please make sure that the object is newed before using it.

    #0 in \simpleadder_monitor_after::predictor at simpleadder_monitor.sv:127
    #1 in \simpleadder_monitor_after::run_phase at simpleadder_monitor.sv:114

    where, the line 127 is sa_tx.out = sa_tx.ina + sa_tx.inb;
    line 114 is predictor();

    3, Another question is regarding the configuration file, such as simpleadder_configuration.sv. What is that used for?

    Again, thank you.

    1. Thank you for your comment Angie.

      About the thrid question, right now, it is used for nothing. I put it there intially because I wanted to show off some configurability, but then I ended up doing nothing with it. I will remove it soon.

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  10. Hi Pedro,

    I get “Test Fail” when simulating the code with Mentor graphics Questasim 10.1c. With Synopsys VCS it is successful. May i know what is the reason behind why it failing with Questa ?

    Thanks and Regards,
    Prasanna

  11. Hi Pedro,

    Firstly thanks for the brilliant tutorial that you have worked on. Keep up the good work !

    Have you tried using VCS 2014.03 ? I get following Error:

    Warning-[ACC_CLI_ON] ACC/CLI capabilities enabled
    ACC/CLI capabilities have been enabled for the entire design. For faster
    performance enable module specific capability in pli.tab file

    Parsing design file ‘/home/pervez/UVM/uvm-1.1c/src/uvm.sv’
    Parsing included file ‘uvm_pkg.sv’.
    Parsing included file ‘/home/pervez/UVM/uvm-1.1c/src/uvm_macros.svh’.
    Parsing included file ‘/home/pervez/UVM/uvm-1.1c/src/macros/uvm_version_defines.svh’.
    Back to file ‘/home/pervez/UVM/uvm-1.1c/src/uvm_macros.svh’.
    Parsing included file ‘/home/pervez/UVM/uvm-1.1c/src/macros/uvm_message_defines.svh’.
    Back to file ‘/home/pervez/UVM/uvm-1.1c/src/uvm_macros.svh’.
    Parsing included file ‘/home/pervez/UVM/uvm-1.1c/src/macros/uvm_phase_defines.svh’.
    ……..
    ……..
    Back to file ‘/home/charlie/UVM/uvm-1.1c/src/uvm.sv’.
    Parsing design file ‘simpleadder_tb_top.sv’
    Parsing included file ‘./code/simpleadder_pkg.sv’.
    Parsing included file ‘/home/charlie/UVM/uvm-1.1c/src/uvm_macros.svh’.
    Back to file ‘./code/simpleadder_pkg.sv’.
    Parsing included file ‘./code/simpleadder_sequencer.sv’.

    Error-[SE] Syntax error
    Following verilog source has syntax error :
    “./code/simpleadder_sequencer.sv”, 1: token is ‘uvm_sequence_item’
    class simpleadder_transaction extends uvm_sequence_item;
    ^

    1 warning
    1 error
    CPU time: 3.101 seconds to compile

    Any help would be appreciated.

  12. Hi Author,
    Files have been moved from the github-link mentioned. Please update it. Not able to download source files.
    Thanks

  13. Thanks for an excellent Introduction to UVM. Unfortunately I am not able to download the code from your github site. Do I need to register before downloading. Please educate me.

  14. Hi, here is the typo

    module simpleadder_tb_top;
    import uvm_pkg::*;
    import simpleadder_pkg::*; // <- need to import the pkg

    otherwise will get error

    # UVM_FATAL @ 0: reporter [NOCOMP] No components instantiated. You must either instantiate at least one component before calling run_test or use run_test to do so. To run a test using run_test, use +UVM_TESTNAME or supply the test name in the argument to run_test(). Exiting simulation.

  15. Hi Pedro, great guide! I’m a newbie to UVM. For some reason I wasn’t able to download the files. It just redirected me to a 404 error webpage. Is there any other way to get the files?

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