Due to the lack of UVM tutorials for complete beginners, I decided to create a guide that will assist a novice in building a verification environment using this methodology. I will not focus on verification techniques nor in the best practices in verifying a digital design, this guide was thought in helping you to understand the UVM API and in helping you to successfully compile a complete environment.
The simulator used is Synopsys VCS but the testbench should compile in any HDL simulator that supports SystemVerilog.
The code for the environment can be download in this GitHub repository: https://github.com/pedro-araujo/uvm-testbench-tutorial-simple-adder
As digital systems grow in complexity, verification methodologies get progressively more essential. While in the early beginnings, digital designs were verified by looking at waveforms and performing manual checks, the complexity we have today don’t allow for that kind of verification anymore and, as a result, designers have been trying to find the best way to automate this process.
The SystemVerilog language came to aid many verification engineers. The language featured some mechanisms, like classes, covergroups and constraints, that eased some aspects of verifying a digital design and then, verification methodologies started to appear.
UVM is one of the methodologies that were created from the need to automate verification. The Universal Verification Methodology is a collection of API and proven verification guidelines written for SystemVerilog that help an engineer to create an efficient verification environment. It’s an open-source standard maintained by Accellera and can be freely acquired in their website.
By mandating a universal convention in verification techniques, engineers started to develop generic verification components that were portable from one project to another, this promoted the cooperation and the sharing of techniques among the user base. It also encouraged the development of verification components generic enough to be easily extended and improved without modifying the original code.
All these aspects contributed for a reduced effort in developing new verification environments, as designers can just reuse testbenches from previous projects and easily modify the components to their needs.
These series of webpages will provide a training guide for verifying a basic adder block using UVM. The guide will assume that you have some basic knowledge of SystemVerilog and will require accompaniment of the following resources:
- Book “SystemVerilog for Verification: A Guide to Learning the TestBench Language Features“, by Chris Spear
- Book “Comprehensive Functional Verification: The Complete Industry Cycle“, by John Goss
This guide will be divided in 3 different parts:
- The first part, starting on chapter 1, will explain the operation of the device under test (DUT): the inputs, the outputs and the communication bus
- The second part, starting on chapter 2, will give a brief overview of a generic verification environment and the approach into verifying the DUT
- The third part, starting on chapter 3, will start to describe a possible UVM testbench to be used with our DUT with code examples. It’s important to consult to the external material in order to better understand the mechanism behind the testbench.