This training guide will focus on showing how we can build a basic UVM environment, so the device under test was kept very simple in order to emphasize the explanation of UVM itself.
The DUT used is a simple ALU, limited to a single operation: the add operation. The inputs and outputs are represented in Figure 1.1.
Figure 1.1: Representation of the DUT’s inputs/outputs
This DUT takes two values of 2 bits each, ina and inb, sums them and sends the result to the output out. The inputs are sampled to the signal of en_i and the output is sent at the same time en_o is signalled.
The operation of the DUT is represented as a timing diagram and as a state machine in Figure 1.2.
Figure 1.2: Operation of the DUT
The code for this DUT can be found here:
Hello Pedro,
Your blog has been really helpful for me as I could not find a much simpler explanation of UVM on the net. Currently, I am working on creating a UVM Environment for DDR3 and facing a lot of issues. Can you please get in touch with me via email?
Thanks,
Subrat
Opearation of DUT image is missing. Please upload it.
Pedro
Can you please explain me why you are doing shift operation on temporary variables.
And in Verilog design module there is never an initial block.
Initial blocks are part of TestBench.
Kindly reply..
The initial block will initialize the signals to a certain known state. The same can be achieved with an initialization statement, see http://stackoverflow.com/a/10016566.
IMO, modules should have a reset signal and their internal registers should reset to a known state. Had the module a reset signal, I bet it’s registers would be assigned the values in the initial block. This case, maybe for simplicity, it has been omitted.
Kind regards.
The DUT has 2 bit inputs that arrive serially. In most examples, the 2 bits are available in the same cycle as the enable but in this particular case you get one bit of the input in the same clock cycle as the enable bit. The other input bit is received in the subsequent clock cycle. The shift operation is required to accommodate this DUT functionality.
GitHub link not working!?
Code can be downloaded from here
https://github.com/naragece/uvm-testbench-tutorial-simple-adder
Was anyone able to get that simpleadder.v?
Code can be downloaded from here
https://github.com/naragece/uvm-testbench-tutorial-simple-adder
Thanks!
Hello pedro,
i was struggling to understand UVM concept , this is proper and structured
and other thing i am not able to access the codes
the link you gave posts the error
Code can be downloaded from here
https://github.com/naragece/uvm-testbench-tutorial-simple-adder
The code is not available
Code can be downloaded from here
https://github.com/naragece/uvm-testbench-tutorial-simple-adder
Hi, I think the code in adder.v is for a counter and not an adder.
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