Master’s Thesis

This thesis’ project was proposed by Synopsys Portugal and it’s going to be carried out under the Integrated Master’s Degree in Electrical and Computer Engineering of the Faculdade de Engenharia da Universidade do Porto.

Subject: Development of a reconfigurable multi-protocol verification environment using UVM methodology

Team:

  • Teacher Supervisor: José Carlos Alves (jca [at] fe.up.pt)
  • Company Supervisors: Luis Cruz (lcruz [at] synopsys.com) & Domingos Terra (dterra [at] synopsys.com)

During the last decades, electronic circuits have grown in complexity and in production costs which compelled engineers to research and develop new methods to verify the electronic design in more comprehensive, detailed and efficient ways.

The UVM methodology is one of the results of the increasing need of digital verification. It’s is designed in a way that allows to structure the verification environment in a reconfigurable architecture, so it can be possible to reuse the same environment across multiple technologies. This methodology is an industry standard recognized by Accellera System Initiative and it’s comprised of a library for the SystemVerilog language (IEEE 1800) and a set of verification guidelines.

The purpose of this work is to take advantage of the best features of UVM and develop a reconfigurable verification environment that supports multiple protocols with minimal development effort. The project will start with the analysis of an existing environment used in a specific technology and then followed by an analysis of the verification techniques that could be used across different protocols.

The goals defined for this project are:

  • Analysis of an existing verification environment and removal of all design logic specific to the original protocol
  • Revision of the verification environment in order to support multiple protocols
  • Creation of generic blocks to support the revised environment
  • Configuration and application of the generic environment to another existent protocol

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