Master’s Thesis
This thesis’ project was proposed by Synopsys Portugal and it’s going to be carried out under the Integrated Master’s Degree in Electrical and Computer Engineering of the Faculdade de Engenharia da Universidade do Porto.
Subject: Development of a reconfigurable multi-protocol verification environment using UVM methodology
Team:
- Teacher Supervisor: José Carlos Alves (jca \[at\]fe.up.pt)
- Company Supervisors: Luis Cruz (lcruz \[at\]synopsys.com) & Domingos Terra (dterra \[at\]synopsys.com)
During the last decades, electronic circuits have grown in complexity and in production costs which compelled engineers to research and develop new methods to verify the electronic design in more comprehensive, detailed and efficient ways.
The UVM methodology is one of the results of the increasing need of digital verification. It’s is designed in a way that allows to structure the verification environment in a reconfigurable architecture, so it can be possible to reuse the same environment across multiple technologies. This methodology is an industry standard recognized by Accellera System Initiative and it’s comprised of a library for the SystemVerilog language (IEEE 1800) and a set of verification guidelines.
The purpose of this work is to take advantage of the best features of UVM and develop a reconfigurable verification environment that supports multiple protocols with minimal development effort. The project will start with the analysis of an existing environment used in a specific technology and then followed by an analysis of the verification techniques that could be used across different protocols.
The goals defined for this project are:
- Analysis of an existing verification environment and removal of all design logic specific to the original protocol
- Revision of the verification environment in order to support multiple protocols
- Creation of generic blocks to support the revised environment
- Configuration and application of the generic environment to another existent protocol
Work plan
The objective of this project is to develop a reconfigurable verification environment that supports multiple protocols using the UVM methodology.
The first step will be to study and analyze the existing verification environment in order to see how it’s structured and to identify what components will have to be replaced. Then, with basis on that study, it will be proposed and discussed possible modifications to be applied to the studied system. After the discussion, the chosen approach will be implemented in the environment. Finally, to prove it’s working, the envinroment will verify a platform yet to be defined.
The distribution of the work throughout the semester is described on the following table:
| Task | Description | Start | Finish |
|---|---|---|---|
| Task 1 | Study of the existing UVM environment | 3 Feb | 21 Feb |
| Task 2 | Proposal of possible implementations | 24 Feb | 28 Feb |
| Task 3 | Implementation | 3 Mar | 2 May |
| Task 4 | Aplication of the researched solution to an existing platform | 5 May | 16 May |
| Task 5 | Writing of the dissertation | 19 May | 6 June |
The following figure represents the Gantt chart of the work plan:
The project will be realized in the offices of Synopsys Porto using the company’s resources. It’s foreseen the usage of the tools:
- VCS: Verilog Compiled code Simulator - Synopsys’ HDL compiler and simulator. Verilog and SystemVerilog code will be compiled with this tool.
- DVE: Discovery Visualization Environment - It’s an advanced debugger and waveform visualization environment from Synopsys. This tool will be used to debug the developed environments.
- UVM Reference Implementation. The UVM API that is freely available at Accellera’s website: http://www.accellera.org/downloads/standards/uvm
The following references are going to be consulted for this project:
- Accellera’s UVM User’s Guide 1.1
- Accellera’s UVM 1.1 Class Reference
- Verification Academy’s UVM Cookbook
- Book “SystemVerilog for Verification: A Guide to Learning the TestBench Language Features”, by Chris Spear
- Book “Comprehensive Functional Verification: The Complete Industry Cycle”, by John Goss
Preliminary report
This is the preliminary report that details how the work was planned for the semester and that contains some initial research about hardware verification languages and the evolution of verification methodologies.
Progress Report 1 - 16th of February
This is the first progress report of my master’s thesis. It’s the first of many more that I’ll keep posting as I’ll progress through the work.
You can find the link to the document here:
Progress Report 1 - 16th of February
Progress Report 2 - 7th of March
You can find here the second progress report:
Progress Report 2 - 7th of March
Progress Report 3 - 16th of March
Third progress report:
Progress Report 3 - 16th of March
Progress Report 4 - 2nd of April
Fourth progress report:
Progress Report 4 - 2nd of April
Progress Report 5 – 30th of April
Fifth progress report:
Progress Report 5 – 30th of April
Progress Report 6 – 6th of June
Sixth progress report:
Progress Report 6 – 6th of June
Final Document
The final document of the Master’s Thesis can be found here.