The last month and half that I have been studying the UVM methodology, I noticed that of all the guides and tutorials about UVM available throughout the internet, none of them reached to a complete beginner in verification.
Before starting this thesis, my knowledge of verification was very limited, it was narrowed to a simple direct tests, hand-written stimuli, and that was it. It was quite hard to find something that I could start on.
As a result, I started writing a guide that approaches verification with SystemVerilog and UVM from the ground zero. In this guide, it’s explained the most essential features and API of UVM and how can you successfully compile a complete verification environment using SystemVerilog and UVM.
You can find the guide here: http://colorlesscube.com/uvm-guide-for-beginners/