After 5 long months of working on this project, the document is finally complete. It can be found in the usual Master’s Thesis section of this blog, or it can be accessed directly here.
Year: 2014
6th Progress Report available
The 6th progress report can be accessed here:
http://colorlesscube.com/progress-report-6-6th-of-june/
A few weeks ago, it was suggested by the professor José Carlos Alves to use the verification environment to verify a model of an audio codec AC97. This week, all the necessary components were completed and the testbench was demonstrated.
There aren’t any major difficulties to report, it deadline is getting closer and it’s time to start writing all the necessary documentation.
PS.: Thanks Daniel for reminding me to keep this page updated.
Fifth progress report posted
The fifth progress report can be seen here:
http://colorlesscube.com/masters-thesis/progress-report-5-30th-of-april/
I started to structure the chapters of the final document that will contain the description of my project. I also started to write a draft for each chapter in order to ease the process of writing for the next few weeks.
Fourth progress report available
This report can be found in the usual place, under the Master’s Thesis section:
http://colorlesscube.com/masters-thesis/progress-report-4-2nd-of-april/
Published an UVM guide for beginners
The last month and half that I have been studying the UVM methodology, I noticed that of all the guides and tutorials about UVM available throughout the internet, none of them reached to a complete beginner in verification.
Before starting this thesis, my knowledge of verification was very limited, it was narrowed to a simple direct tests, hand-written stimuli, and that was it. It was quite hard to find something that I could start on.
As a result, I started writing a guide that approaches verification with SystemVerilog and UVM from the ground zero. In this guide, it’s explained the most essential features and API of UVM and how can you successfully compile a complete verification environment using SystemVerilog and UVM.
You can find the guide here: http://colorlesscube.com/uvm-guide-for-beginners/
Posted third progress report
The third report can be found here: http://colorlesscube.com/masters-thesis/progress-report-3-16th-of-march/
I started to develop a verification environment for an I2C bus basing myself on the research I did. I’m also delayed about two weeks compared to the original plan but I expect to keep up with this delay very soon.
In the next few days, the UVM guide I have been writing will be published in this website along with the code for educational purposes.
Posted the second progress report
I posted the second progress report for my thesis in the Master’s Thesis section.
Nothing much to report, just the expected study of some verification concepts that I didn’t have and the completion of the analysis of an existing UVM envinroment used by Synopsys.
You can find the document here: http://colorlesscube.com/masters-thesis/progress-report-2-7th-of-march/
Updated Master’s Thesis section
I’ve added a description of my master’s thesis, as well the work plan for the semester and the preliminary report with some initial research.
I will keep this website updated with sections of my thesis that I will be writing and guides about verification methodologies.
Hello, world
Hello, welcome to my website.
I’m a student in the last year of my Master’s degree in Electrical and Computer Engineering, currently working on my master’s thesis.
I created this website to publish content related to my master’s thesis. My thesis is related to verification methodologies of digital hardware designs, you can check more information here. I’ll keep this website updated with work planning and progress reports, in addition to guides and information about digital verification.
Feel free to check and consult any information you see available.